1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a three-dimensional (3D) semiconductor device having one or more nanowire channel structures by performing an anneal process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
One process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins, and these trenches are typically formed in the substrate during the same process operation for processing simplicity. In some cases, the trenches are desirably designed with the same pitch (for better resolution during lithography) and they are formed to the same depth and width (for processing simplicity), wherein the depth of the trenches is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. In other cases, modern integrated circuit products may have multiple regions that each have different fin pitches. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
In one particular prior art process flow, a layer of silicon/germanium (SiGe) having a germanium concentration of about 30% was formed above a silicon substrate. Thereafter, the trenches were formed to define the Si/SiGe fins. Then, a layer of silicon dioxide was formed in the trenches and above the fins. Typically, due to the high aspect ratio of the trenches found in modern devices, the silicon dioxide material selected for filling the trenches had to be a material that exhibited relatively good fill capabilities, frequently, a silicon dioxide material made using a so-called HARP (High Aspect Ratio) process available from Applied Materials. In general, the HARP process employs an ozone-TEOS process chemistry to produce what will be referred to as “HARP silicon dioxide.” Other higher quality oxides, like oxides made using the well-known HDP (High Density Plasma) process, did not exhibit the necessary fill capabilities for use on modern or future devices. Unfortunately, the HARP silicon dioxide material was of relatively poor quality as it contained a relatively high amount of dangling bonds and OH groups that, upon heating, form water molecules. Thus, when the trenches were filled with a HARP silicon dioxide material, an anneal process was performed on the devices in an attempt to improve the quality of the HARP silicon dioxide, e.g., an attempt was made to drive off moisture, eliminate pinholes, etc. Typically, a relatively long anneal was then performed on the device, e.g., about 1050° C. for a duration of about 30 minutes in a traditional furnace with a nitrogen ambient. The relatively long anneal process effectively bakes out the water and other species in the layer of HARP silicon dioxide and otherwise passivates the bonds such that the layer of HARP silicon dioxide is not conductive (so as to reduce or eliminate leakage currents). In some cases, a spike anneal of about 1050° C. may have been performed on such a device in a room-air ambient with the 30% germanium concentration for the same purposes, but such a spike anneal was not as effective in reducing undesirable leakage currents.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production cost relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices.
The present disclosure is directed to various methods of forming a three-dimensional (3D) semiconductor device having one or more nanowire channel structures.